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LH1687
LH1687
DESCRIPTION
The LH1687 is a 240-output TFT-LCD source driver IC used in such products as TV sets. The LH1687 samples and holds three video signals of R, G and B by sample and hold circuits synchronized with the CK, and simultaneously outputs the LCD drive voltage from all output pins.
240-output TFT-LCD Source Driver IC
PIN CONNECTIONS
264-PIN TCP TOP VIEW
1 OS1
FEATURES
* Number of LCD drive outputs : 240 * Output circuit form : Push pull output * Power save function : By setting the LCD drive output in a high-impedance condition, the current source of the LCD drive output circuit is cut off, which makes low power operation possible * Sampling timing : Normal sampling operation and 3-point simultaneous sampling operation can be selected * Video signal setting : Available for stripe pixel array panels and delta pixel array panels using mode setting circuit * Sampling clock frequency : 25 MHz (MAX.) * Cascade connection * Sampling sequence : Output shift direction can be selected OS1/OS240 or OS240/OS1 * Output amplitude voltage : 4.8 Vp-p (at 5.0 V supply voltage) * Supply voltages - VCCL (for logic system) : +3.0 to +5.5 V - VCCA (for LCD drive system) : +3.0 to +5.5 V * Operating temperature : -30 to + 85 C * Package : 264-pin TCP (Tape Carrier Package)
VCCA VCCL GNDA GNDL TST5 VC VB VA MODE PS RL SAM CTR CK SPIO SPOI TEST4 TEST3 TEST2 TEST1 GNDL GNDA VCCL VCCA
264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241
CHIP SURFACE
240 OS240
NOTE :
Doesn't prescribe TCP outline.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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LH1687
PIN DESCRIPTION
PIN NO. 1 to 240 241, 264 242, 263 243, 262 244, 261 245 to 248 249 250 251 252 253 254 255 256 257 to 259 260 SYMBOL OS1-OS240 VCCA VCCL GNDA GNDL TST1-TST4 SPOI SPIO CK CTR SAM RL PS MODE VA, VB, VC TST5 I/O O - - - - I I/O I/O I I I I I I I I DESCRIPTION LCD drive output pins Power supply pins for LCD drive circuit Power supply pins for logic circuit Ground pins for LCD drive system Ground pins for logic system IC test pins Start pulse input/cascade output pin Start pulse input/cascade output pin Horizontal shift clock input pin LCD drive circuit operation selection pin Sampling mode selection pin Sampling sequence selection pin Power save mode setting pin Video signals form setting pin Video signal input pins IC test pin
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LH1687
BLOCK DIAGRAM
SPOI 249 SPIO 250 CK 251 CTR 252 SAM 253 RL 254 CONTROL LOGIC SAMPLING SIGNAL CREATION CIRCUIT 1 240 BI-DIRECTIONAL SHIFT REGISTER
TST1 245 TST2 246 TST3 247 1
240
MODE 256 VA 257 VB 258 VC 259 MODE SETTING CIRCUIT
SAMPLE AND HOLD CIRCUIT
1
240
PS 255 TST4 248 TST5 260
BIAS GENERATION CIRCUIT 1
OUTPUT CIRCUIT
240
241 264 VCCA VCCA
242 263
243 262
244 261
1
240 OS240
VCCL VCCL GNDA GNDA GNDL GNDL OS1
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LH1687
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK Control Logic Bi-directional Shift Register Sampling Signal Creation Circuit Mode Setting Circuit Sample and Hold Circuit FUNCTION Used to create signals necessary for each operation mode setting and sampling signal creation circuits, etc. Used as transfer circuit of video sampling start signals. It is possible to set the direction of sampling start signal sequence OS1/OS240 or OS240/OS1 by setting the R/L pin. Used to create the sampling signals corresponding to each output pin based on the sampling start signals transferred by the bi-directional shift register. Used to set the form of the video signals to be sent to the sample and hold circuits. Used to sample the video signals input from the mode setting circuit at the timing of the sampling signals and hold the sampling data until the next sampling operation.
Bias Generation Circuit Used to generate bias voltage necessary for output circuits. Output Circuit The circuit consists of a push-pull output operational amplifier and outputs the voltage corresponding to the data held in the sample and hold circuits.
INPUT/OUTPUT CIRCUITS
VCCL
I
To Internal Circuit
GNDL
Applicable pins CK, CTR, MODE
Fig. 1 Input Circuit (1)
VCCA
I
To Internal Circuit
GNDA
Applicable pins VA, VB, VC
Fig. 2 Input Circuit (2)
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LH1687
VCCL
VCCL
I
To Internal Circuit
GNDL
Applicable pins SAM, RL, PS, TST1-TST4
Fig. 3 Input Circuit (3)
VCCA
VCCA
I
To Internal Circuit
GNDA
Applicable pin TST5
Fig. 4 Input Circuit (4)
Pch Tr
VCCL
I
O
Output Signal
Output Control Signal Nch Tr GNDL
VCCL
To Internal Circuit
GNDL
Applicable pins SPIO, SPOI
Fig. 5 Input/Output Circuit
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LH1687
VCCA Operational Amplifier O
+ -
From Internal Circuit
GNDA
Applicable pins OS1-OS240
Fig. 6 Output Circuit
FUNCTIONAL DESCRIPTION Pin Functions
SYMBOL VCCL VCCA GNDL GNDA TST1-TST4 TST5 FUNCTION Used as power supply pin for logic circuit, connected to +3.0 to +5.0 V. Used as power supply pin for LCD drive circuit, connected to +3.0 to +5.0 V. Must be set to VCCL VCCA. Used as ground pin for logic circuit, connected to 0 V. Used as ground pin for LCD drive circuit, connected to 0 V. Used as input pins for IC testing, connected to VCCL (high level). Used as input pins for IC testing, connected to VCCA (high level). Used as input/output pins of cascade operation start signal. SPIO SPOI SPIO becomes input pin of operation start signal and SPOI becomes output pin of operation start signal of next IC when set to R/L = "H". SPOI becomes input pin of operation start signal and SPIO becomes output pin of operation start signal of next IC when set to R/L = "L". Used as horizontal shift clock input pin. Video signals are sampled in order at the rising and falling edge of CK. Used as input pin of selecting video signal sampling circuits and selecting input signal of output operational amplifiers. Used as input pin for setting the selecting of normal sampling operation or 3-point simultaneous sampling operation. For normal sampling operation, video signals are sampled into sample and hold circuits every 1 LCD drive output. SAM For 3-point simultaneous sampling operation, video signals are sampled into sample and hold circuits every 3 LCD drive outputs simultaneously. For either operation, sampling signals are shifted at every rising and falling edge of horizontal shift clock of CK pin (half clock), and their sampling period is equal to the period of one clock.
CK CTR
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LH1687
SYMBOL FUNCTION Used as input pin for setting the shift direction of video signal sampling sequence and the selecting input/output of SPIO/SPOI pins. RL Video signals are sampled in order of OS1/OS240, set SPIO to input of operation start signal and set SPOI to output of operation start signal of next IC when set RL to "H". Video signals are sampled in order of OS240/OS1, set SPOI to input of operation start signal and set SPIO to output of operation start signal of next IC when set RL to "L". Used as input pin for setting of power save mode. LCD drive output pins output voltage corresponding to video signals held in the sample PS and hold circuits when set PS to "H". The LH1687 is set low power mode by setting high-impedance condition and cutting off current source of LCD drive outputs when set PS to "L". Used as input pin for setting video signals for sampling in the sample and hold circuits. By mode setting circuit, video signals are sampled and output in order of VB, VA, and VC when set to "H" and in order of VC, VB, and VA when set to "L" with respect to OS1 to OS240 . Used as input pins of video signals. VB, VA, VC, VB, VA, VC or VC, VB, VA, VC, VB, VA are input with respect to LCD drive outputs OS1, OS2, OS3, OS238, OS239, OS240 by MODE pin setting condition. Used as LCD drive output pins. OS1-OS240 Voltage corresponding to video signals held in the sample and hold circuits is output when set to PS = "H", and becomes high-impedance condition when set to PS = "L".
MODE
VA VB VC
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LH1687
Functional Operations
(1) Examples of Cascade Sequence When RL = "H"
Horizontal Scanning Direction Cascade Sequence 1st Start Signal SPIO SPOI Cascade Sequence 2nd SPIO SPOI Cascade Sequence n SPIO
OS1
OS240
OS1
OS240
OS1
OS240
TFT-LCD Panel
(n : number of LH1687 used)
When RL = "L"
Horizontal Scanning Direction
TFT-LCD Panel
(n : number of LH1687 used)
OS240
OS1
OS240
OS1
OS240
OS1
Start Signal
SPOI
SPIO
SPOI
SPIO
SPOI
SPIO
Cascade Sequence 1st
Cascade Sequence 2nd
Cascade Sequence n
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LH1687
(2) Video Signal Mode Setting Function With MODE pin condition, it is possible to set the form of video signals corresponding to each output pin by selecting the mode setting circuit. When MODE = "H"
Mode Setting Circuit
VB
VA
VC
VB
VA
VC
VB
VA
VC
OS1 OS2 OS3 OS4 OS5 OS6 Output Circuit
OS238 OS239 OS240
When MODE = "L"
Mode Setting Circuit
VC
VB
VA
VC
VB
VA
VC
VB
VA
OS1 OS2 OS3 OS4 OS5 OS6 Output Circuit
OS238 OS239 OS240
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LH1687
(3) Output Circuit Type The LH1687 samples video signals by the sample and hold circuits of 2 systems and outputs the voltage corresponding to the sampled data by the input switching operational amplifiers with push-pull output buffer. Sample and hold circuits and output circuits are as shown in the diagram below.
When CTR = "H", the LH1687 samples the data to system A of the sample and hold circuits and outputs the voltage corresponding to the voltage sampled by capacitor B of system B. When CTR = "L", the LH1687 samples the data to system B of the sample and hold circuits and outputs the voltage corresponding to the voltage sampled by capacitor A of system A.
System A of Sample and Hold Circuits Sampling Signal A GNDA Capacitor A Video Signal Capacitor B - Sampling Signal B GNDA Operational Amplifier + Output Buffer +1 +2 Output Pin
System B of Sample and Hold Circuits
Therefore, it is usually necessary to repeat the sampling operation and output operation by exchanging CTR signal ("H" to "L" or "L" to "H") for every start signal. While CTR signal is set to "H" or "L" several times
for start signal, the same voltage is output continuously. The output voltage corresponds to the data sampled by the previous sampling operation. Timing of operation is as follows.
Start signal
CTR
System A System B
Sampling 1 Output 0
Output 1 Sampling 2
Sampling 3 Output 2
Sampling 3' Output 2
Output 3' Sampling 4
Also, there is a power save function which makes high-impedance of the output pin and a reduction in the current of operational amplifiers possible when
set to PS = "L", but careful attention must be paid to the displaying quality etc. when using it.
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LH1687
(4) Examples of LCD Panel Connection With the video signal mode setting function of (2), it is possible to connect LCD panel to the stripe pixel array panel and delta pixel array panel as shown in the following examples. (a) Example of Stripe Pixel Array Panel Connection
Video Signals G R B
VA VB VC
LH1687
OS1 OS2 OS3
OS238 OS239 OS240
1st Line
R
G
B
R
B
R
G
B
MODE = "H"
Sampling Data
2nd Line
R
G
B
R
B
R
G
B
MODE = "H"
3rd Line
R
G
B
R
B
R
G
B
MODE = "H"
Connection of video signal input pins
Video signal input pin Video signal VA G VB R VC B
Setting of video signals that are to be sampled by output circuits and MODE pin condition
OS (3n + 1) OS (3n + 2) OS (3n + 3) MODE pin setting 1st LINE R G B "H" 2nd LINE R G B "H" 3rd LINE R G B "H" AFTER 4th LINE R G B "H"
(n = 0, 1, 2, , 79)
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LH1687
(b) Example of Delta Pixel Array Panel Connection
Video Signals G R B
VA VB VC
LH1687
OS1 OS2 OS3
OS238 OS239 OS240
1st Line
R
G
B
R
B
R
G
B
MODE = "H"
Sampling Data
2nd Line
B
R
G
B
R
G
B
R
G
MODE = "L"
3rd Line
R
G
B
R
B
R
G
B
MODE = "H"
Connection of video signal input pins
Video signal input pin Video signal VA G VB R VC B
Setting of video signals that are to be sampled by output circuits and MODE pin condition
OS (3n + 1) OS (3n + 2) OS (3n + 3) MODE pin setting 1st LINE R G B "H" 2nd LINE B R G "L" 3rd LINE R G B "H" AFTER 4th LINE B and R are alternately selected. R and G are alternately selected. G and B are alternately selected. "L" and "H" are alternately selected.
(n = 0, 1, 2, , 79) NOTES :
* Set the MODE pin condition during blanking period. * Input the horizontal shift clock signal of CK pin by shifting the phase for each line according to the shift of the pixels connected to the same source bus line. If the pixels connected to the same source bus line are shifted by half the pixels, change the clock phase 90 degrees. Clock phase must be changed during blanking period.
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LH1687
Outline of Operation Timing
(1) Overall Operation Timing Video signals of one horizontal scanning period are sampled into the sample and hold circuits at the timing of the internal sampling pulses of each
output circuit, and data corresponding to the sampled data are output.
Horizontal Blanking Period
Effective Display Period
Video Signals
One Horizontal Scanning Period (j)
One Horizontal Scanning Period (j + 1)
Start Pulse (Horizontal Scanning Start Pulse) S1
S240 (Internal Sampling Signals) PS (Power Save Signal) OS1-OS240 Output (LCD Drive Outputs) High-Z
Sampling Data (j - 1) Output
Output High-Z
Sampling Data (j) Output
Output High-Z
Sampling Data (j + 1) Output
(2) Timing of Video Signal Sampling If the normal sampling operation and cascade sequence is 1st, the video signal sampling (internal sampling signal Sn (n = 1, 2, , 240)) is started at the
rising edge of first clock after falling edge of start pulse.
CK 0 Start Pulse (Horizontal Scanning Start Pulse) S1 (Normal Sampling Operation, Cascade Sequence 1st) S2 Video Signal Sampling Start 1 2
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LH1687
Timing Chart for Normal Sampling Operation
(1) When RL = "H"
CK 0 SPIO S1 S2 1 2 120 121
S239 S240 SPOI
NOTE : S1 to S240 are internal sampling signals of video signal. (2) When RL = "L"
CK 0 SPOI S240 S239 1 2 120 121
S2 S1 SPIO
NOTE : S1 to S240 are internal sampling signals of video signal.
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LH1687
Timing Chart for 3-point Simultaneous Sampling Operation
(1) When RL = "H"
CK 0 SPIO S1-S3 S4-S6 1 2 40 41
S235-S237 S238-S240 SPOI
NOTE : S1 to S240 are internal sampling signals of video signal. (2) When RL = "L"
CK 0 SPOI S238-S240 S235-S237 1 2 40 41
S4-S6 S1-S3 SPIO
NOTE : S1 to S240 are internal sampling signals of video signal.
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LH1687
Timing Chart for PS Operation
CK 1 PS 1 2
OS1-OS240
Sampling Data Output Period
Output Hi-impedance Period
Sampling Data Output Period
Timing Chart for CTR Operation
CK 1 CTR 2 1 2
OS1-OS240
Sampling of System A & Output Period System B
Sampling of System B & Output Period System A
Sampling of System A & Output Period System B
PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC has some power supply pins, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. Therefore, when connecting the power supply, set the logic system input pins (SPIO, SPOI, CK, CTR, MODE, SAME, RL, PS, TST1, TST2, TST3, TST4) after supplying the voltage to the logic system power supply pin (VCCL), and next supplying the voltage to the LCD drive system power supply pin (VCCA). Finally, set the LCD drive system input pins (VA, VB, VC, TST5). When disconnecting the power supply, follow the reverse sequence. When connecting or disconnecting the power supply follow the recommended sequence shown here.
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LH1687
Power Suplly of Logic System
Input of Logic System
Power Supply of LCD Drive System
Input of LCD Drive System
Connecting The Power Supply or Input Signals
Disconnecting The Power Supply or Input Signals
Setting of Input pins Since 5 pins of SPIO, SPOI, CK, CTR, and MODE of the input pins are not pulled up or pulled down in the IC, never use these 5 pins in the "OPEN" condition. Since VA, VB, and VC pins are for inputting video signals, necessary video signals must always be input. Except for VA, VB, VC, SPIO, SPOI, CK, CTR, and MODE, all other input pins are pulled up in the IC. However, to preventing malfunction due to noise etc., avoid using the "OPEN" condition whenever possible, and set to "H" level or "L" level. Input video signals Input video signals are target for analog signals (continuous signals). The input band of video signals is applicable up to the maximum of 12.5 MHz.
Bypass capacitor If the noise of a logic system is superposed on analog circuits such as the sample and hold circuits, analog characteristics (such as output voltage deviation and dynamic range, etc.) may deteriorate. For this reason, insert bypass capacitors of about 1 F between VCCL and GNDL, VCCA and GNDA. Fully evaluate and determine the value of bypass capacitors with them actually mounted on the LCD module. Maximum ratings When connecting or disconnecting the power supply, this IC must be used within the range of the absolute maximum ratings.
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LH1687
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage SYMBOL VCCL VCCA VINL VINA Storage temperature TSTG APPLICABLE PINS VCCL VCCA CK, CTR, SPIO, SPOI, MODE, RL, SAM, PS, TST1-TST4 TST5, VA, VB, VC RATING -0.3 to +7.0 -0.3 to +7.0 -0.3 to VCCL + 0.3 -0.3 to VCCA + 0.3 -45 to +125 UNIT V V V V C 1, 2 NOTE
Input voltage
NOTES :
1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to GNDL and GNDA (0 V).
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage SYMBOL VCCL VCCA VINL VINA Operating temperature TOPR APPLICABLE PINS VCCL VCCA CK, CTR, SPIO, SPOI, MODE, RL, SAM, PS, TST1-TST4 TST5, VA, VB, VC RATING +3.0 to +5.5 +3.0 to +5.5 0 to VCCL 0 to VCCA -30 to +85 UNIT V V V V C 1, 2 NOTE
Input voltage
NOTES :
1. The applicable voltage on any pin with respect to GNDL and GNDA (0 V). 2. Ensure that voltages are set such that VCCL VCCA.
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LH1687
ELECTRICAL CHARACTERISTICS DC Characteristics
(Unless otherwise specified, GNDL = GNDA = 0 V, VCCL = +3.3 V, VCCA = +5.0 V, TOPR = -30 to +85 C)
PARAMETER Input "Low" voltage Input "High" voltage Input voltage Input "Low" current SYMBOL CONDITIONS VIL VIHL VINA IIL1 IIL2 Input "High" current Dynamic range Deviations between output voltage pins Supply current (In operation mode) Supply current (In power save mode) Supply current IIHL IIHA Vp-p VOD ICCA1 VCCA ICCA2 ICCL1 VCCL 1.5 100 A mA 3 2 VIN = VCCL VIN = VCCA VIN = 0 V APPLICABLE PINS MIN. TYP. MAX. UNIT. CK, CTR, SPIO, SPOI, 0 0.3VCCL V MODE, RL, SAM, PS 0.7VCCL VCCL V VA, VB, VC CK, CTR, SPIO, SPOI, MODE, VA, VB, VC RL, SAM, PS CK, CTR, SPIO, SPOI, MODE, RL, SAM, PS VA, VB, VC VA, VB, VC OS1-OS240 0.1 -20 6.0 0 VCCA 10 400 10 10 VCCA - 0.1 20 V A A A A V mV mA 1 2 NOTE
NOTES :
1. Start signal : Cycle tSP = 63.5 s, "H" period width tWSP = 80 ns. CTR signal : Cycle tCTR = 127.0 s, "H" period width tWCTR = 63.5 s. Change from "H" to "L" or "L" to "H" is synchronized with start pulse during blanking period. CK signal : Frequency fCK = 12.5 MHz (duty = 50%) VA = VB = VC = 0.1 V to VCCA - 0.1 V Connect all other pins to high level. Voltage difference between the average voltage of all OS output pins in the chip and the output voltage of each OS output pin. TA = 25 C 2. Start signal : Cycle tSP = 63.5 s, "H" period width tWSP = 80 ns. CTR signal : Cycle tCTR = 127.0 s, "H" period width tWCTR = 63.5 s. Change from "H" to "L" or "L" to "H" is synchronized with start pulse during blanking period. CK signal : Frequency fCK = 12.5 MHz (duty = 50%) Connect VA, VB, and VC pins to VCCA. Connect all other pins to high level. 3. Start signal : Cycle tSP = 63.5 s, "H" period width tWSP = 80 ns. CTR signal : Cycle tCTR = 127.0 s, "H" period width tWCTR = 63.5 s. Change from "H" to "L" or "L" to "H" is synchronized with start pulse during blanking period. CK signal : Frequency fCK = 12.5 MHz (duty = 50%) Pin to be set to GND : PS Connect VA, VB, and VC pins to VCCA. Connect all other pins to high level.
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LH1687
AC Characteristics
(Unless otherwise specified, GNDL = GNDA = 0 V, VCCL = +3.3 V, VCCA = +5.0 V, TOPR = -30 to +85 C)
PARAMETER Clock frequency "H" level clock width "L" level clock width Input rise time Input fall time Start pulse width Start pulse setup time Start pulse hold time Start pulse output delay time PS signal setup time CTR signal setup time Output transfer delay time Output rise time Output fall time Power save delay time Power save rise time Power save fall time SYMBOL CONDITIONS SAM = "H" fCK SAM = "L" tWHC tWLC tRC tFC tWSP tSUSP tHSP tDSP tSUPS tSUCTR tDO tR tF tDOP tROP tFOP OS1-OS240 CL = 15 pF PS CTR 1 -------2fCK 1 -------2fCK 5.0 5.0 5.0 3.0 5.0 5.0 SAM = "H" SAM = "L" SAM = "H" SAM = "L" SAM = "H" SAM = "L" SAM = "H" SAM = "L" SPIO, SPOI 1 -------fCK 10.0 15.0 20.0 SPIO, SPOI, CK APPLICABLE PINS MIN. TYP. MAX. 12.5 7.0 CK 30.0 50.0 30.0 50.0 10.0 20.0 10.0 20.0 UNIT MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s s s 2 1 NOTE
SPIO, SPOI, CK
NOTES :
1. Start signal : Cycle tSP = 63.5 s, "H" period width tWSP = 80 ns. CTR signal : Cycle tCTR = 127.0 s, "H" period width tWCTR = 63.5 s. Change from "H" to "L" or "L" to "H" is synchronized with start pulse during blanking period. CK signal : Frequency fCK = 12.5 MHz (duty = 50%) Connect VA, VB, and VC pins to VCCA. Connect all other pins to VCCL. Capacity of output load CL = 150 pF 2. Add load resistor (10 k$) to NOTE 1. Load resistor is connected to GNDA or VCCA level as follows.
Output Pin 10 k$ GNDA VCCA 10 k$ Output Pin 150 pF GNDA 150 pF
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LH1687
Timing Chart
1 fCK
90%
tWHC
90% 90%
tWLC
CK
10% 10%
1
10%
2
10%
3
tSUSP
90% 90%
tHSP
tRC
tFC
SPIO Input (SPOI)
tWSP
CK
10%
LAST - 2 tDSP
LAST - 1
10%
LAST tDSP
1'
2'
3'
SPIO Output (SPOI)
90% 10%
90%
90% 10%
CK
10%
tSUPS
tSUPS
90%
PS
10%
tDOP tFOP
90%
tDOP tROP
90% 10%
OS1-OS240
Sampling Data Output
Output High-impedance
10%
90%
90% 10%
CK
10%
tSUCTR
90%
tSUCTR
90% 10%
CTR
10%
tDO tFO
90%
tDO tRO
90% 10% 10%
OS1-OS240
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